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Espressif Systems /ESP32-H2 /HP_SYS /CPU_PERI_TIMEOUT_CONF

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Interpret as CPU_PERI_TIMEOUT_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CPU_PERI_TIMEOUT_THRES0 (CPU_PERI_TIMEOUT_INT_CLEAR)CPU_PERI_TIMEOUT_INT_CLEAR 0 (CPU_PERI_TIMEOUT_PROTECT_EN)CPU_PERI_TIMEOUT_PROTECT_EN

Description

CPU_PERI_TIMEOUT configuration register

Fields

CPU_PERI_TIMEOUT_THRES

Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain.
CPU_PERI_TIMEOUT_INT_CLEAR

Set this bit as 1 to clear timeout interrupt
CPU_PERI_TIMEOUT_PROTECT_EN

Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data